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SST32HF3242 데이터시트(PDF) 2 Page - Silicon Storage Technology, Inc

부품명 SST32HF3242
상세설명  Multi-Purpose Flash Plus SRAM ComboMemory
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제조업체  SST [Silicon Storage Technology, Inc]
홈페이지  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST32HF3242 데이터시트(HTML) 2 Page - Silicon Storage Technology, Inc

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Preliminary Specifications
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282
SST32HF1622C / SST32HF1642C / SST32HF3242C
©2005 Silicon Storage Technology, Inc.
S71253-03-000
5/05
The SST32HFx2/x2C devices are suited for applications
that use both flash memory and (P)SRAM memory to store
code or data. For systems requiring low power and small
form factor, the SST32HFx2/x2C devices significantly
improve performance and reliability while lowering power
consumption when compared with multiple chip solutions.
The SST32HFx2/x2C inherently use less energy during
Erase and Program operations than alternative flash tech-
nologies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since, for
any given voltage range, SuperFlash technology uses less
current to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies.
SuperFlash technology provides fixed Erase and Program
times independent of the number of Erase/Program cycles
that have occurred. Therefore the system software or hard-
ware does not have to be modified or de-rated as is neces-
sary with alternative flash technologies, whose Erase and
Program times increase with accumulated Erase/Program
cycles.
Device Operation
The SST32HFx2/x2C use BES1#, BES2 and BEF# to con-
trol operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
SRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to VIHC (Logic High) or
when BEF# is high and BES2 is low.
Concurrent Read/Write Operation
The SST32HFx2/x2C provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. See Figure 26 for a flowchart. The following
table lists all valid states.
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST32HFx2/x2C devices is
controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when OE# is high. Refer to Figure 6 for
further details.
CONCURRENT READ/WRITE STATE TABLE
Flash
SRAM
Program/Erase
Read
Program/Erase
Write


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