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STE10A 데이터시트(PDF) 9 Page - STMicroelectronics |
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STE10A 데이터시트(HTML) 9 Page - STMicroelectronics |
9 / 82 page STE10/100A Pin description 9/82 3 17 28 42 C-BEB3 C-BEB2 C-BEB1 C-BEB0 I/O Bus command and byte enable 4 IDSEL I Initialization device select. This signal is asserted when the host issues configuration cycles to the STE10/100A. 18 FRAME# I/O Asserted by PCI bus master during bus tenure 20 IRDY# I/O Master device is ready to begin data transaction 21 TRDY# I/O Target device is ready to begin data transaction 22 DEVSEL# I/O Device select. Indicates that a PCI target device address has been decoded 23 STOP# I/O PCI target device request to the PCI master to stop the current transaction 24 PERR# I/O Data parity error detected, driven by the device receiving data 25 SERR# O/D Address parity error 26 PAR I/O Parity. Even parity computed for AD[31:0] and C/BE[3:0]; master drives PAR for address and write data phase, target drives PAR for read data phase. Boot ROM/EEPROM interface 56~59 61~66 80~86 87 BrA0~3 BrA4~9 BrA10~15 BrA16/ LED M2 - Fd/Col I/O ROM data bus Provides up to 128Kbit EPROM or flash-ROM application space. This pin can be programmed as mode 2 LED display for full duplex or collision status. It will be driven (LED on) continually when a full duplex configuration is detected, or it will be driven at a 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. 67~71 72 73 74 BrD0~4 BrD5/EDO BrD6/EDI BrD7/ECK O O/I O/O O/O BootROM data bus (0~7) EDO: Data output of serial EEPROM, data input to STE10/100A EDI: Data input to serial EEPROM, data output from STE10/100A ECK: Clock input to serial EEPROM, sourced by STE10/100A 76 EECS O Chip select of serial EEPROM 77 BrCS# O BootROM chip select 78 BrOE# O BootROM read output enable for flash ROM application 79 BrWE# O BootROM write enable for flash ROM application. Table 1. Pin description (continued) Pin no. Name Type Description |
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