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MC10E431FN 데이터시트(PDF) 6 Page - ON Semiconductor

부품명 MC10E431FN
상세설명  5V ECL 3-Bit Differential Flip-Flop
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10E431FN 데이터시트(HTML) 6 Page - ON Semiconductor

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MC10E431, MC100E431
http://onsemi.com
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Table 8. AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 13)
Symbol
Characteristic
−40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fMAX
Maximum Toggle Frequency
1.1
GHz
tPLH
tPHL
Propagation Delay to Output
CLK
R
S
550
500
500
700
725
725
850
975
975
550
550
550
700
725
725
850
925
925
550
550
550
700
725
725
850
925
925
ps
tS
Setup Time
D
R (Note 14)
S (Note 14)
250
1100
1100
0
700
700
200
1000
1000
0
700
700
200
1000
1000
0
700
700
ps
tH
Hold Time
D
250
0
200
0
200
0
ps
tPW
Minimum Pulse Width
CLK
400
400
400
ps
tskew
Within-Device Skew (Note 15)
50
50
ps
tJITTER
Random Clock Jitter (RMS)
< 1
< 1
< 1
ps
VPP
Input Voltage Swing
(Differential Configuration)
150
1000
150
1000
150
1000
mV
tr/tf
Rise/Fall Times
(20−80%)
250
450
700
275
450
650
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
13.10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
14.These setup times define the minimum time the CLK or SET/RESET input must wait after the assertion of the RESET/SET input to assure
the proper operation of the flip-flop.
15.Within-device skew is defined as identical transitions on similar paths through a device.


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