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MC74LCX573_05 데이터시트(Datasheet) 1 Page - ON Semiconductor

부품명 MC74LCX573_05
상세내용  Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)
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제조사  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2005
May, 2005 − Rev. 7
1
Publication Order Number:
MC74LCX573/D
MC74LCX573
Low−Voltage CMOS
Octal Transparent Latch
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX573 is a high performance, non−inverting octal
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX573 inputs to be safely driven from 5.0 V devices.
The MC74LCX573 contains 8 D−type latches with 3−state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn
inputs enters the latches. In this condition, the latches are transparent,
i.e., a latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW transition
of LE. The 3−state standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The LCX573 flow through design facilitates easy PC
board layout.
Features
Designed for 2.3 to 3.6 V V
CC Operation
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
I
OFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
20
1
1
20
MARKING
DIAGRAMS
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW
= Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20
DW SUFFIX
CASE 751D
LCX573
AWLYYWWG
LCX
573
ALYW
G
G
TSSOP−20
DT SUFFIX
CASE 948E
SOEIAJ−20
M SUFFIX
CASE 967
74LCX573
AWLYWWG
1
1
1
20
1
20
20
20
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
http://onsemi.com




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