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MC74ACT273DTR2G 데이터시트(PDF) 1 Page - ON Semiconductor |
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1 / 8 page © Semiconductor Components Industries, LLC, 2005 December, 2005 − Rev. 6 1 Publication Order Number: MC74AC273/D MC74AC273, MC74ACT273 Octal D Flip−Flop The MC74AC273/74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW−to−HIGH clock transition, is transferred to the corresponding flip−flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Features • Ideal Buffer for MOS Microprocessor or Memory • Eight Edge-Triggered D Flip−Flops • Buffered Common Clock • Buffered, Asynchronous Master Reset • See MC74AC377 for Clock Enable Version • See MC74AC373 for Transparent Latch Version • See MC74AC374 for 3-State Version • Outputs Source/Sink 24 mA • ′ACT273 Has TTL Compatible Inputs • Pb−Free Packages are Available* Pinout: 20−Lead Packages Conductors 19 20 18 17 16 15 14 2 1 34567 VCC 13 8 12 9 11 10 Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND (Top View) MODE SELECT-FUNCTION TABLE Operating Mode Inputs Outputs MR CP Dn Qn Reset (Clear) L X X L Load ′1′ H H H Load ′0′ H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOEIAJ−20 SUFFIX M CASE 967 http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION 1 TSSOP−20 SUFFIX DT CASE 948E SOIC−20WB SUFFIX DW CASE 751D 1 1 See general marking information in the device marking section on page 6 of this data sheet. DEVICE MARKING INFORMATION 20 20 20 PDIP−20 SUFFIX N CASE 738 1 20 PIN ASSIGNMENT PIN D0−D7 FUNCTION Data Inputs MR Master Reset CP Clock Pulse Input Q0−Q7 Data Outputs Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 CP MR Logic Symbol |
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