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MC100EPT24MNR4 데이터시트(PDF) 1 Page - ON Semiconductor |
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MC100EPT24MNR4 데이터시트(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 8 1 Publication Order Number: MC100EPT24/D MC100EPT24 3.3VLVTTL/LVCMOS to Differential LVECL Translator Description The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium. Features • 350 ps Typical Propagation Delay • Maximum Input Clock Frequency > 1.0 GHz Typical • The 100 Series Contains Temperature Compensation • Operating Range: VCC = 3.0 V to 3.6 V; VEE = −3.6 V to −3.0 V; GND = 0 V • PNP LVTTL Input for Minimal Loading • Q Output will Default HIGH with Input Open • Pb−Free Packages are Available SOIC−8 D SUFFIX CASE 751 MARKING DIAGRAMS* TSSOP−8 DT SUFFIX CASE 948R ALYWG G KA24 1 8 1 8 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION 1 8 KPT24 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 (Note: Microdot may be in either location) A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package |
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