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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CAT24FC256GXETE13 데이터시트(PDF) 5 Page - Catalyst Semiconductor |
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CAT24FC256GXETE13 데이터시트(HTML) 5 Page - Catalyst Semiconductor |
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5 / 12 page  Discontinued Part CAT24FC256 5 Doc. No. 1040, Rev. K © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24FC256 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The CAT24FC256 uses the next three bits as address bits. The address bits A2, A1 and A0 allow Figure 4. Acknowledge Timing Figure 5. Slave Address Bits ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER as many as eight devices on the same bus. These bits must compare to their hardwired input pins. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24FC256 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC256 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24FC256 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. When the CAT24FC256 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC256 will continue to transmit I2C BUS PROTOCOL 1 0 1 0 A2 A1 A0 R/W |
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