© Semiconductor Components Industries, LLC, 2006

October, 2006 − Rev. 6

1

Publication Order Number:

MC14001UB/D

MC14001UB, MC14011UB

UB−Suffix Series

CMOS Gates

The UB Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired. The UB set of

CMOS gates are inverting non−buffered functions.

Features

Low−Power Schottky TTL Load Over the Rated Temperature Range

Suffix Devices

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

−0.5 to +18.0

V

Input or Output Voltage Range

(DC or Transient)

V

Input or Output Current

(DC or Transient) per Pin

± 10

mA

Power Dissipation, per Package

(Note 1)

500

mW

Ambient Temperature Range

−55 to +125

°C

Storage Temperature Range

−65 to +150

°C

Lead Temperature

(8−Second Soldering)

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

Unused inputs must always be tied to an appropriate logic voltage level

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

1

14

PDIP−14

P SUFFIX

CASE 646

MC140xxUBCP

AWLYYWWG

SOIC−14

D SUFFIX

CASE 751A

1

14

140xxUG

AWLYWW

http://onsemi.com

xx

= Specific Device Code

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

G= Pb−Free Package