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MC14521BCP 데이터시트(PDF) 6 Page - ON Semiconductor

부품명 MC14521BCP
상세설명  24?뭆tage Frequency Divider
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC14521BCP 데이터시트(HTML) 6 Page - ON Semiconductor

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MC14521B
http://onsemi.com
6
Figure 5. RC Oscillator Stability
Figure 6. RC Oscillator Frequency as a
Function of RTC and C
−55
−25
0
25
50
75
100
125
8.0
4.0
0
−4.0
−8.0
−12
−16
TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY
TEST CIRCUIT
FIGURE 7
VDD = 15 V
10 V
5.0 V
RTC = 56 kW,
C = 1000 pF
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
{
100
50
20
10
5.0
1.0
2.0
0.1
0.2
0.5
1.0 k
10 k
100 k
1.0 m
0.0001
0.001
0.01
0.1
RTC, RESISTANCE (OHMS)
C, CAPACITANCE (mF)
VDD = 10 V
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
TEST CIRCUIT
FIGURE 7
f AS A FUNCTION
OF C
(RTC = 56 kW)
(RS = 120 k)
Figure 7. RC Oscillator Circuit
Figure 8. Functional Test Circuit
OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
IN 1
IN 2
R
VDD VDD
VSS
VSS
VDD
RS
RTC
C
Q18
Q19
Q20
Q21
Q22
Q23
Q24
OUT 1
OUT 2
IN 1
IN 2
R
VDD
VDD
VSS VSS
PULSE
GENERATOR
FUNCTIONAL TEST SEQUENCE
A test function (see Figure 8) has been included
for the reduction of test time required to exercise all
24 counter stages. This test function divides the
counter into three 8−stage sections, and 255
counts are loaded in each of the 8−stage sections
in parallel. All flip−flops are now at a logic “1”. The
counter is now returned to the normal 24−stages in
series configuration. One more pulse is entered into
Input 2 (In 2) which will cause the counter to ripple
from an all “1” state to an all “0” state.
Inputs
Outputs
Comments
Reset
In 2
Out 2
VSS
VDD
Q18
thru
Q24
Counter is in three 8−stage sections
in parallel mode Counter is reset. In 2
and Out 2 are connected together.
1
0
0
VDD
GND
GND
VDD
0
0
1
1
First “0” to “1” transition on In 2,
Out 2 node.
0
1
0
1
255 “0” to “1” transitions are clocked
into this In 2, Out 2 node.
1
1
1
The 255th “0” to “1” transition.
0
0
0
0
1
1
1
0
1
Counter converted back to 24−stages
in series mode.
1
0
1
Out 2 converts back to an output.
0
1
0
Counter ripples from an all “1” state
to an all “0” stage.


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