Datasheet

A2TPMI Datasheet Rev4

Page 14 of 21

Rev. Oct 2003

LATCHUP AVOIDANCE

Junction isolated CMOS circuits inherently include a parasitic 4 layer (PNPN) structure which has char-

acteristics similar to a thyristor (SCR). Under certain circumstances this junction may be triggered into a

low impedance state, resulting in excessive supply current, which can thermally destroy the circuit.

To avoid this condition, no voltage greater than 0.3 V beyond the supply rails should be applied to any

pin. In general the ATPMI supplies must be established either at the same time or before any signals

are applied to the inputs. If this is not possible the drive circuits must limit the input current flow to

maximum 5mA to avoid latchup. In general the device has to be operated with a 100 nF capacitor in

parallel to the power supply.

SOLDERING

The TPMI is a lead-free component and fully complies with the ROHS regulations, especially with exist-

ing roadmaps of lead-free soldering. The terminations of the TPMI sensor consist of nickel plated Kovar

and gold finish. Hand soldering is recommended.