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ADF4113HVBCPZ-RL7 데이터시트(PDF) 9 Page - Analog Devices |
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ADF4113HVBCPZ-RL7 데이터시트(HTML) 9 Page - Analog Devices |
9 / 20 page ADF4113HV Rev. 0 | Page 9 of 20 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 14. SW1 and SW2 are normally closed switches (NC in Figure 14). SW3 is normally open (NO in Figure 14). When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. BUFFER TO R COUNTER REFIN 100kΩ NC SW2 SW3 NO NC SW1 POWER-DOWN CONTROL Figure 14. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 15. It is followed by a two-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler. AVDD AGND 500Ω 500Ω 1.6V BIAS GENERATOR RFINA RFINB Figure 15. RF Input Stage PRESCALER (P/P + 1) Together with the A and B counters, the dual-modulus prescaler (P/P + 1) enables the large division ratio, N, to be realized by N = BP + A The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and CMOS B counters. The pre- scaler is programmable; it can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. A AND B COUNTERS The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 200 MHz or less (for AVDD = 5 V). Thus, with an RF input frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not. Pulse Swallow Function The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is fVCO = [(P × B) + A]fREFIN/R where: fVCO = output frequency of external voltage controlled oscillator (VCO). P = preset modulus of dual-modulus prescaler. B = preset divide ratio of binary 13-bit counter (3 to 8191). A = preset divide ratio of binary 6-bit swallow counter (0 to 63). fREFIN = output frequency of the external reference frequency oscillator. R = preset divide ratio of binary 14-bit programmable reference counter (1 to 16,383). 13-BIT B COUNTER 6-BIT A COUNTER PRESCALER P/P + 1 FROM RF INPUT STAGE MODULUS CONTROL N= BP + A LOAD LOAD TO PFD Figure 16. A and B Counters R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase fre- quency detector (PFD). Division ratios from 1 to 16,383 are allowed. |
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