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AD8324JRQ-EVAL 데이터시트(PDF) 6 Page - Analog Devices |
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AD8324JRQ-EVAL 데이터시트(HTML) 6 Page - Analog Devices |
6 / 16 page AD8324 Rev. A | Page 6 of 16 PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS TOP VIEW (Not to Scale) AD8324 1 2 3 4 5 15 14 13 12 11 16 17 20 19 18 67 8 9 10 GND GND GND VIN+ VIN– RAMP VOUT+ VOUT– BYP NC TOP VIEW (Not to Scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD8324 TXEN SDATA VCC CLK VIN+ SLEEP BYP NC VOUT+ NC = NO CONNECT GND GND GND GND VIN– GND RAMP VOUT– GND VCC DATEN Figure 5. 20-Lead LFCSP Figure 6. 20-Lead QSOP Table 6. Pin Function Descriptions Pin No. Pin No. 20-Lead LFCSP 20-Lead QSOP Mnemonic Description 1, 2, 5, 9, 18, 19 1, 3, 4, 7, 11, 20 GND Common External Ground Reference. 17, 20 2, 19 VCC Common Positive External Supply Voltage. 3 5 VIN+ Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor. 4 6 VIN– Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor. 6 8 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous and simultaneously enables the register for serial data load). 7 9 SDATA Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal register with the MSB (most significant bit) first. 8 10 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. 10 12 SLEEP Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 μA. A Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part. 12 14 BYP Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor). 13 15 VOUT– Negative Output Signal. Must be biased to VCC. See Figure 23. 14 16 VOUT+ Positive Output Signal. Must be biased to VCC. See Figure 23. 15 17 RAMP External RAMP Capacitor (Optional). 16 18 TXEN Logic 0 disables forward transmission. Logic 1 enables forward transmission. |
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