전자부품 데이터시트 검색엔진 |
|
AD8330ACPZ-R2 데이터시트(PDF) 3 Page - Analog Devices |
|
AD8330ACPZ-R2 데이터시트(HTML) 3 Page - Analog Devices |
3 / 32 page AD8330 Rev. C | Page 3 of 32 SPECIFICATIONS VS = 5 V, TA = 25°C, CL = 12 pF on OPHI and OPLO, RL = ∞, VDBS = 0.75 V, VMODE = high, VMAG = O/C (0.5 V), VOFST = 0 V, differential operation, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT INTERFACE Pin INHI, Pin INLO Full-Scale Input VDBS = 0 V, differential drive ±1.4 ±2 V VDBS = 1.5 V ±4.5 ±6.3 mV Input Resistance Pin-to-pin 800 1 k 1.2 k Ω Input Capacitance Either pin to COMM 4 pF Voltage Noise Spectral Density f = 1 MHz, VDBS = 1.5 V; inputs ac-shorted 5 nV/√Hz Common-Mode Voltage Level 3.0 V Input Offset Pin OFST connected to Pin COMM 1 mV rms Drift 2 μV/°C Permissible CM Range1 0 VS V Common-Mode AC Rejection f = 1 MHz, 0.1 V rms −60 dB f = 50 MHz −55 dB OUTPUT INTERFACE Pin OPHI, Pin OPLO Small Signal –3 dB Bandwidth 0 V < VDBS < 1.5 V 150 MHz Peak Slew Rate VDBS = 0 1500 V/μs Peak-to-Peak Output Swing ±1.8 ±2 ±2.2 V VMAG ≥ 2 V (peaks are supply limited) ±4 ±4.5 V Common-Mode Voltage Pin CNTR O/C 2.4 2.5 2.6 V Voltage Noise Spectral Density f = 1 MHz, VDBS = 0 62 nV/√Hz Differential Output Impedance Pin-to-pin 120 150 180 Ω HD22 VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ −62 dBc HD32 VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ −53 dBc OUTPUT OFFSET CONTROL Pin OFST AC-Coupled Offset CHPF on Pin OFST (0 V < VDBS < 1.5 V) 10 mV rms High-Pass Corner Frequency CHPF = 3.3 nF, from OFST to CNTR (scales as 1/CHPF) 100 kHz COMMON-MODE CONTROL Pin CNTR Usable Voltage Range 0.5 4.5 V Input Resistance From Pin CNTR to VS/2 4 kΩ DECIBEL GAIN CONTROL VDBS, CMGN, and MODE pins Normal Voltage Range CMGN connected to COMM 0 to 1.5 V Elevated Range CMGN O/C (VCMGN rises to 0.2 V) 0.2 to 1.7 V Gain Scaling Mode high or low 27 30 33 mV/dB Gain Linearity Error 0.3 V ≤ VDBS ≤ 1.2 V −0.35 ±0.1 +0.35 dB Absolute Gain Error VDBS = 0 −2 ±0.5 +2 dB Bias Current Flows out of Pin VDBS 100 nA Incremental Resistance 100 MΩ Gain Settling Time to 0.5 dB Error VDBS stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V 250 ns Mode Up/Down Pin MODE Mode Up Logic Level Gain increases with VDBS, MODE = O/C 1.5 V Mode Down Logic Level Gain decreases with VDBS 0.5 V LINEAR GAIN INTERFACE Pin VMAG, Pin CMGN Peak Output Scaling, Gain vs. VMAG See Circuit Description section 3.8 4.0 4.2 V/V Gain Multiplication Factor vs. VMAG Gain is nominal when VMAG = 0.5 V ×2 Usable Input Range 0 5 V Default Voltage VMAG O/C 0.48 0.5 0.52 V Incremental Resistance 4 kΩ Bandwidth For VMAG ≥ 0.1 V 150 MHz |
유사한 부품 번호 - AD8330ACPZ-R2 |
|
유사한 설명 - AD8330ACPZ-R2 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |