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SY88883V 데이터시트(PDF) 5 Page - Micrel Semiconductor |
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SY88883V 데이터시트(HTML) 5 Page - Micrel Semiconductor |
5 / 8 page 5 SY88883V Micrel, Inc. M9999-081005 hbwhelp@micrel.com or (408) 955-1690 DETAILED DESCRIPTION The SY88883V low-power limiting post amplifier operates from a single +3.3V or +5V power supply, over temperatures from –40 °C to +85°C. Signals with data rates up to 3.2Gbps and as small as 10mVPP can be amplified. Figure 1 shows the allowed input voltage swing. The SY88883V generates an SD output. SD LVL sets the sensitivity of the input amplitude detection. Input Amplifier/Buffer The SY88883V’s inputs are internally terminated with 50 Ω to an internal reference voltage (V REF). VREF is typically 1.3V below V CC. Unless not affected by this internal termination scheme, upstream devices need to be AC-coupled to the SY88883V’s inputs. Figure 2 shows a simplified schematic of the input stage. The high-sensitivity of the input amplifier allows signals as small as 10mVPP to be detected and amplified. The input amplifier allows input signals as large as 1800mVPP. Input signals are linearly amplified with a typically 38dB differential voltage gain. Since it is a limiting amplifier, the SY88883V outputs typically 800mVPP voltage-limited waveforms for input signals that are greater than 10mVPP. Applications requiring the SY88883V to operate with high- gain should have the upstream TIA placed as close as possible to the SY88883V’s input pins to ensure the best performance of the device. Output Buffer The SY88883V’s CML output buffer is designed to drive 50 Ω lines. The output buffer requires appropriate termination for proper operation. An external 50 Ω resistor to V CC or equivalent for each output pin provides this. Figure 3 shows a simplified schematic of the output stage and includes an appropriate termination method. Of course, driving a downstream device with a CML input that is internally terminated with 50 Ω to V CC eliminates the need for external termination. As noted in the previous section, the amplifier outputs typically 800mVPP waveforms across 25Ω total loads. The output buffer, thus, switches typically 16mA tail- current. Figure 4 shows the power supply current measurement which excludes the 16mA tail-current. Signal Detect The SY88883V generates a chatter-free signal detect (SD) open-collector TTL output with internal 5k Ω pull-up resistor as shown in Figure 5. SD is used to determine that the input amplitude large enough to be considered a valid input. SD asserts high if the input amplitude rises above the threshold set by SD LVL and deasserts low otherwise. Typically 4.6dB SD hysteresis is provided to prevent chattering. Signal Detect-Level Set A programmable signal detect-level set pin (SD LVL) sets the threshold of the input amplitude detection. Connecting an external resistor between V CC and SDLVL sets the voltage at SD LVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between V CC and V REF as shown in Figure 6. If desired, an appropriate external voltage may be applied rather than using a resistor. The smaller the external resistor, implying a smaller voltage difference from SD LVL to VCC, lowers the SD sensitivity. Hence, larger input amplitude is required to assert SD. “Typical Operating Characteristics” shows the relationship between the input amplitude detection sensitivity and the SD LVL setting resistor. Hysteresis The SY88883V provides typically 4.6dB SD electrical hysteresis. By definition, a power ratio measured in dB is 10log(power ratio). Power is calculated as V2 IN/R for an electrical signal. Hence, the same ratio can be stated as 20log(voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and, hence, the ratios change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the data sheet. The SY88883V provides typically 2.3dB SD optical hysteresis. As the SY88883V is an electrical device, this data sheet refers to hysteresis in electrical terms. With 4.6dB SD hysteresis, a voltage factor of 1.7 is required to assert SD from its deassert level. |
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