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FDS8817NZ 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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FDS8817NZ 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page FDS8817NZ Rev.C www.fairchildsemi.com 2 Electrical Characteristics T J = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V 30 V ΔBV DSS ΔT J Breakdown Voltage Temperature Coefficient ID = 250μA, referenced to 25°C 20 mV/°C IDSS Zero Gate Voltage Drain Current VDS = 24V, VGS = 0V 1 μA IGSS Gate to Source Leakage Current VGS = ±20V, VDS = 0V ±10 μA On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250μA 1 1.8 3 V ΔV GS(th) ΔT J Gate to Source Threshold Voltage Temperature Coefficient ID = 250μA, referenced to 25°C –6 mV/°C rDS(on) Static Drain to Source On Resistance VGS = 10V, ID = 15A 5.4 7 m Ω VGS = 4.5V, ID = 12.6A 7.0 10 VGS = 10V, ID = 15A TJ = 125°C 7.5 11 gFS Forward Transconductance VDS = 5V, ID = 15A 54 S (Note 2) Dynamic Characteristics Ciss Input Capacitance VDS = 15V, VGS = 0V, f = 1MHz 1805 2400 pF Coss Output Capacitance 335 445 pF Crss Reverse Transfer Capacitance 200 300 pF Rg Gate Resistance f = 1MHz 1.4 Ω Switching Characteristics td(on) Turn-On Delay Time VDD = 15V, ID = 15A VGS = 10V, RGEN = 6Ω 11 22 ns tr Rise Time 13 26 ns td(off) Turn-Off Delay Time 25 40 ns tf Fall Time 7 14 ns Qg Total Gate Charge VGS = 0V to 10V VDD = 15V ID = 15A 32 45 nC Qg Total Gate Charge VGS = 0V to 5V 17 24 nC Qgs Gate to Source Charge 6 nC Qgd Gate to Drain “Miller” Charge 7 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage VGS = 0V, IS = 2.1A (Note 2) 0.8 1.2 V trr Reverse Recovery Time IF = 15A, di/dt = 100A/μs 24 36 ns Qrr Reverse Recovery Charge 15 23 nC a) 50°C/W when mounted on a 1in2 pad of 2 oz copper. b) 125°C/W when mounted on a minimum pad . Notes: 1. RθJA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design. 2. Pulse Test: Pulse Width < 300 us, Duty Cycle < 2%. 3. The diode connected between the gate and source serves only as protection against ESD . No gate overvoltage rating is implied. 4. Starting TJ = 25°C, L = 3mH, IAS = 11A, VDD = 30V, VGS = 10V. |
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