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CD3206BB 데이터시트(PDF) 10 Page - NXP Semiconductors |
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CD3206BB 데이터시트(HTML) 10 Page - NXP Semiconductors |
10 / 18 page Philips Semiconductors Product specification FB2031 9-bit latched/registered/pass-thru Futurebus+ transceiver 1995 May 25 10 AC ELECTRICAL CHARACTERISTICS (Industrial) B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CD = 30pF, RU = 16.5Ω Tamb = –40 to +85°C, VCC = 5V±10%, CD = 30pF, RU = 16.5Ω UNIT MIN TYP MAX MIN MAX tPLH tPHL Propagation delay (thru mode) An to Bn Waveform 1, 2 1.0 1.0 3.0 2.7 5.0 4.0 1.5 1.5 5.7 4.5 ns tPLH tPHL Propagation delay (transparent latch) An to Bn Waveform 1, 2 1.0 1.0 3.2 3.1 5.0 4.2 1.5 1.5 5.5 5.0 ns tPLH tPHL Propagation delay LCAB to Bn Waveform 1, 2 2.0 1.5 4.0 4.0 5.5 5.5 1.5 1.5 6.5 6.0 ns tPLH tPHL Propagation delay SEL0 or SEL1 to Bn Waveform 1, 2 2.0 1.5 3.5 2.3 5.5 4.5 2.0 1.0 6.1 5.5 ns tPZH tPZL Enable/disable time OEB0 or OEB1 to Bn Waveform 1, 2 1.5 1.2 3.0 2.4 5.0 4.5 1.0 1.0 5.7 5.5 ns tTLH tTHL Output transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.6 2.0 3.0 0.9 0.6 3.0 3.0 ns tSK(o) Output to output skew for multiple channels1 Waveform 3 1.0 0.4 1.6 1.6 ns tSK(p) Pulse skew2 tPHL – tPLH MAX Waveform 2 0.3 1.0 1.5 ns NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). |
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