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AM29DL400B_05 데이터시트(Datasheet) 4 Page - Advanced Micro Devices

부품명 AM29DL400B_05
상세내용  4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
PDF  47 Pages
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
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Am29DL400B
GENERAL DESCRIPTION
The Am29DL400B is an 4 Mbit, 3.0 volt-only flash
memory device, organized as 262,144 words or
524,288 bytes. The device is offered in 44-pin SO
and 48-pin TSOP packages. The word-wide (x16)
data appears on DQ0–DQ15; the byte-wide (x8)
data appears on DQ0–DQ7. This device requires only
a single 3.0 volt VCC supply to perform read, pro-
gram, and erase operations. A standard EPROM
programmer can also be used to program and erase
the device.
The standard device offers access times of 70, 80,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. Standard control
pins—chip enable (CE#), write enable (WE#), and
output enable (OE#)—control read and write opera-
tions, and avoid bus contention issues.
The device requires only a single 3.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for
the program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. Bank 1 contains boot/parame-
ter sectors, and Bank 2 consists of larger, code
sectors of uniform size. The device can improve
overall system performance by allowing a host sys-
t e m to p r og ram o r eras e in on e b an k, th e n
immediately and simultaneously read from the other
bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
Am29DL400B Features
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write tim-
ings. Register contents serve as input to an internal
state machine that controls the erase and program-
ming circuitry. Write cycles also internally latch
addresses and data needed for the programming and
erase operations. Reading data out of the device is
similar to reading from other Flash or EPROM
devices.
Device programming occurs by executing the pro-
g ram co mmand sequ ence. This initiate s the
Embedded Program algorithm—an internal algo-
rithm that automatically times the program pulse
widths and verifies proper cell margin. The Unlock
Bypass mode facilitates faster programming times
by requiring only two write cycles to program data
instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device automatically re-
turns to reading array data.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without
affecting the data contents of other sectors. The de-
vice is fully erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware
sector protection feature disables both program
and erase operations in any combination of the sec-
tors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data
from, or program data to, any sector within that
bank that is not selected for erasure. True back-
ground erase can thus be achieved. There is no need
to suspend the erase operation if the read data is in
the other bank.
The hardware RESET# pin terminates any opera-
tion in progress and resets the internal state
machine to reading array data. The RESET# pin may
be tied to the system reset circuitry. A system reset
would thus also reset the device to reading array
data, enabling the system microprocessor to read
the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte or
word at a time using hot electron injection.




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