AM29LV652DU90RMAF datasheet(12/54 Pages) AMD

부품명	AM29LV652DU90RMAF

상세설명	128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO??Control

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Am29LV652D

24961A5 May 5, 2006

D A TA

SH EE T

enabled for read access until the command register

contents are altered.

See “VersatileIO‰ (VIO) Control” for more informa-

tion. Refer to the AC “Read-Only Operations” on

page 39 table for timing specifications and to Figure

13, on page 39 for the timing diagram. I

CC1 in the DC

Characteristics table represents the active current

specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# (or CE2#) to V

IL, and OE# to VIH.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a byte, instead of four. The “Byte

Program Command Sequence” on page 26 section

contains details on programming data to the device

using both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2, on page 11 indicates

the address space that each sector occupies.

I

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput dur-

ing system production.

If the system asserts V

HH on ACC, the device automat-

ically enters the aforementioned Unlock Bypass mode,

temporarily unprotects any protected sectors, and

uses the higher voltage to reduce the time required for

program operations. The system would use a two-cy-

cle program command sequence as required by the

Unlock Bypass mode. Removing V

HH from ACC re-

turns the device to normal operation. Note that ACC

must not be at V

HH for operations other than acceler-

ated programming, or device damage may result.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” on page 19

and “Autoselect Command Sequence” on page 26

sections for more information.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE#, CE2#, and RESET# are all held at V

CC ± 0.3 V.

(Note that this is a more restricted voltage range than

V

IH.) If CE#, CE2#, and RESET# are held at VIH, but

not within V

CC ± 0.3 V, the device is in the standby

mode, but the standby current is greater. The device

requires standard access time (t

CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I

CC3 in the DC Characteristics (for two Am29LV065 de-

vices) table represents the standby current specifica-

tion.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, CE2#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

I

CC4 in the DC Characteristics (for two Am29LV065 de-

vices) table represents the automatic sleep mode cur-

rent specification.

RESET#: Hardware Reset Pin

RESET# provides a hardware method of resetting the

device to reading array data. When RESET# is driven

low for at least a period of t

RP, the device immediately

terminates any operation in progress, tristates all out-

puts, and ignores all read/write commands for the du-

ration of the RESET# pulse. The device also resets

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated

once the device is ready to accept another command

sequence, to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

SS ± 0.3 V, the device

draws CMOS standby current (I

CC4). If RESET# is held

at V

IL, but not within VSS ± 0.3 V, the standby current is

greater.

RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

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