전자부품 데이터시트 검색엔진 |
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AM29LV652DU12RMAE 데이터시트(PDF) 43 Page - Advanced Micro Devices |
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AM29LV652DU12RMAE 데이터시트(HTML) 43 Page - Advanced Micro Devices |
43 / 54 page May 5, 2006 24961A5 Am29LV652D 41 D A TA SH EE T AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” on page 50 section for more information. 3. CE# can be replaced with CE2# when referring to the second device within the package. Parameter Speed Options JEDEC Std. Description 90R 12R Unit t AVAV t WC Write Cycle Time (Note 1) Min 90 120 ns t AVWL t AS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 50 ns t AHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns t ELWL t CS CE# Setup Time Min 0 ns t WHEH t CH CE# Hold Time Min 0 ns t WLWH t WP Write Pulse Width Min 35 50 ns t WHDL t WPH Write Pulse Width High Min 30 ns t WHWH1 t WHWH1 Byte Programming Operation (Note 2) Typ 5 µs t WHWH1 t WHWH1 Accelerated Byte Programming Operation (Note 2) Typ 4 µs t WHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ 1.6 sec t VHH V HH Rise and Fall Time (Note 1) Min 250 ns t VCS V CC Setup Time (Note 1) Min 50 µs t RB Write Recovery Time from RY/BY# Min 0 ns t BUSY Program/Erase Valid to RY/BY# Delay Min 90 ns |
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