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AM29LV641MH 데이터시트(PDF) 30 Page - Advanced Micro Devices |
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AM29LV641MH 데이터시트(HTML) 30 Page - Advanced Micro Devices |
30 / 60 page 28 Am29LV641MH/L December 21, 2005 DA TA SH EET Figure 6. Program Suspend/Program Resume Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con- trols or timings during these operations. Table 10 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for infor- mation on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are un- available when an erase operation is in progress. Figure 7 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must re- write the command sequence and any additional ad- dresses and commands. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. Program Operation or Write-to-Buffer Sequence in Progress Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors Write Program Resume Command Sequence Read data as required Done reading? No Yes Write address/data XXXh/30h Device reverts to operation prior to Program Suspend Write address/data XXXh/B0h Wait 15 μs |
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