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AM29LV652DU12RMAF 데이터시트(PDF) 30 Page - Advanced Micro Devices |
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AM29LV652DU12RMAF 데이터시트(HTML) 30 Page - Advanced Micro Devices |
30 / 54 page 28 Am29LV652D 24961A5 May 5, 2006 D A TA SH EE T When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” on page 31 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that oc- curs, the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. Figure 4, on page 29 illustrates the algorithm for the erase operation. Refer to the “Erase and Program Op- erations” on page 41 tables in the AC Characteristics section for parameters, and Figure 17, on page 43 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 10, on page 30 shows the address and data requirements for the sec- tor erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must re- write the command sequence and any additional ad- dresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See “DQ3: Sector Erase Timer” on page 33.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to “Write Operation Status” on page 31 for infor- mation on these status bits. Once the sector erase operation begins, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device returns to read- ing array data, to ensure data integrity. Figure 4, on page 29 illustrates the algorithm for the erase operation. Refer to the “Erase and Program Op- erations” on page 41 tables in the AC Characteristics section for parameters, and Figure 17, on page 43 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec- tor erase operation, including the 50 µs time-out pe- riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- imum of 20 µs to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation is suspended, the device en- ters the erase-suspend-read mode. The system can read data from or program data to any sector not se- lected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status infor- mation on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is ac- tively erasing or is erase-suspended. Refer to “Write Operation Status” on page 31 for information on these status bits. |
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