전자부품 데이터시트 검색엔진
Selected language     Korean  ▼
부품명
         상세내용
Preview PDF Download HTML-1page HTML-10pages

AM41DL3234GB45IS 데이터시트(Datasheet) 37 Page - Advanced Micro Devices

부품명 AM41DL3234GB45IS
상세내용  32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
PDF  65 Pages
Scroll/Zoom Zoom In 100% Zoom Out
제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo 

 37 page
background image
36
Am41DL32x4G
November 12, 2001
P R E L IMINARY
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE#f to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 19 to compare out-
puts for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 23 shows the toggle bit timing diagram. Figure
24 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it re-
turns to determine the status of the operation (top of
Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
gr ammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to reading array data (or
to the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 19 shows the status of DQ3 relative to the other
status bits.




Html 페이지

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65 


데이터시트



관련 부품명

부품명상세내용Html View제조사
AM41DL32X8G32 Megabit 4 M x 8-Bit/2 M x 16-Bit CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memory and 8 Mbit 1 M x 8-Bit/512 K x 16-Bit Static RAM 1 2 3 4 5 MoreAdvanced Micro Devices
AM29DL400B_054 Megabit 512 K x 8-Bit/256 K x 16-Bit CMOS 3.0 Volt-only Simultaneous Operation Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29DL322D_0532 Megabit 4 M x 8-Bit/2 M x 16-Bit CMOS 3.0 Volt-only Simultaneous Operation Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29LV400B_034 Megabit 512 K x 8-Bit/256 K x 16-Bit CMOS 3.0 Volt-only Boot Sector Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29DS323D_0632 Megabit 4 M x 8-Bit/2 M x 16-Bit CMOS 1.8 Volt-only Simultaneous Operation Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29DL800B_068 Megabit 1 M x 8-Bit/512 K x 16-Bit CMOS 3.0 Volt-only Simultaneous Operation Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29DL16XD_0616 Megabit 2 M x 8-Bit/1 M x 16-Bit CMOS 3.0 Volt-only Simultaneous Operation Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29BL802C8 Megabit 512 K x 16-Bit CMOS 3.0 Volt-only Burst Mode Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29F400B_064 Megabit 512 K x 8-Bit/256 K x 16-Bit CMOS 5.0 Volt-only Boot Sector Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29LV320D32 Megabit 4 M x 8-Bit/2 M x 16-Bit CMOS 3.0 Volt-only Boot Sector Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices

링크 URL

ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ]  

Alldatasheet는?   |   광고문의    |   운영자에게 연락하기   |   개인정보취급방침   |   즐겨찾기   |   링크교환   |   제조사별 검색
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl