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AM41PDS3224DB35IS 데이터시트(PDF) 11 Page - Advanced Micro Devices |
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AM41PDS3224DB35IS 데이터시트(HTML) 11 Page - Advanced Micro Devices |
11 / 59 page 10 Am41PDS3224D May 13, 2002 P R E L IMINARY MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- ti on. The r egi s t er i s a la tc h us ed to s t or e the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Tables 1–2 list the device bus opera- tions, the inputs and control levels they require, and the resulting output. The following subsections de- scribe each of these operations in further detail. Table 1. Device Bus Operations—SRAM Word Mode, CIOs = V CC Legend: L = Logic Low = V IL, H = Logic High = VIH, VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address Input, Byte Mode, SADD = Flash Sector Address, A IN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = V IL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = V IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = V ACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V HH, all sectors will be unprotected. Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# SA Addr. LB#s (Note 3) UB#s (Note 3) RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 Read from Flash L HX LH X A IN XX H L/H D OUT D OUT XL Write to Flash L HX HL X A IN XX H (Note 4) D IN D IN XL Standby V CC ± 0.3 V HX XX X X X X V CC ± 0.3 V H High-Z High-Z XL Output Disable L L H HH X X L X H L/H High-Z High-Z HH X X X L Flash Hardware Reset X HX X X X X X X L L/H High-Z High-Z XL Sector Protect (Note 5) L HX HL X SADD, A6 = L, A1 = H, A0 = L XX V ID L/H D IN X XL Sector Unprotect (Note 5) L HX HL X SADD, A6 = H, A1 = H, A0 = L XX V ID (Note 6) D IN X XL Temporary Sector Unprotect X HX XX X X X X V ID (Note 6) D IN High-Z XL Read from SRAM H L H L H X A IN LL HX D OUT D OUT H L High-Z D OUT LH D OUT High-Z Write to SRAM H L H X L X A IN LL HL/H D IN D IN H L High-Z D IN LH D IN High-Z |
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