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6 / 63 page 4 Am49DL640BH December 5, 2003 ADV ANCE I N FO RMAT I O N Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................. 54 Write Cycle ............................................................................. 55 Figure 31. Pseudo SRAM Write Cycle—WE# Control .................... 55 Figure 32. Pseudo SRAM Write Cycle— UB#s and LB#s Control................................................................... 56 Flash Erase And Programming Performance . . . 57 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 57 Package Pin Capacitance . . . . . . . . . . . . . . . . . . 57 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 57 pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 58 pSRAM Power on and Deep Power Down . . . . . 58 Figure 33. Deep Power-down Timing............................................. 58 Figure 34. Power-on Timing........................................................... 58 pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 59 Figure 35. Read Address Skew ..................................................... 59 Figure 36. Write Address Skew...................................................... 59 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60 FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 60 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61 |
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