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74VCX162601MTD 데이터시트(PDF) 1 Page - Fairchild Semiconductor

부품명 74VCX162601MTD
상세설명  Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26??Series Resistors in the B-Port Outputs
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
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© 2004 Fairchild Semiconductor Corporation
DS500150
www.fairchildsemi.com
April 1998
Revised October 2004
74VCX162601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and
Outputs and 26
Ω Series Resistors in the B-Port Outputs
General Description
The VCX162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the HIGH-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCX162601 is designed for low voltage (1.4V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCX162601 is also designed with 26
Ω series resistors
in the B-Port outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
Features
s 1.4V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26
Ω series resistors in B-Port outputs
s tPD (A to B)
3.8 ns max for 3.0V to 3.6V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL B outputs)
±12 mA @ 3.0V V
CC
s Uses patented noise/EMI reduction circuitry
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model
> 2000V
Machine model
>200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Order Number
Package Number
Package Description
74VCX162601MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OEAB, OEBA
Output Enable Inputs (Active LOW)
LEAB, LEBA
Latch Enable Inputs
CLKAB, CLKBA
Clock Inputs
CLKENAB, CLKENBA
Clock Enable Inputs
A1–A18
Side A Inputs or 3-STATE Outputs
B1–B18
Side B Inputs or 3-STATE Outputs


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