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ISL5216KI 데이터시트(PDF) 6 Page - Intersil Corporation |
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ISL5216KI 데이터시트(HTML) 6 Page - Intersil Corporation |
6 / 65 page 6 July 8, 2005 Functional Description The ISL5216 is a 4-channel digital receiver integrated circuit offering exceptional dynamic range and flexibility. Each of the four channels consists of a front-end NCO, digital mixer, and CIC-filter block and a back-end FIR, AGC and Cartesian to polar coordinate-conversion block. The parameters for the four channels are independently programmable. Four 17-bit parallel data input busses (A(15:-1), B(15:-1), C(15:-1) and D(15:-1)) and four pairs of serial data outputs (SDxA, SDxB, SDxC, and SDxD; x = 1 or 2) are provided. Each input can be connected to any or all of the internal signal processing channels, Channels 0, 1, 2 and 3. The output of each channel can be routed to any of the serial outputs. Outputs from more than one channel can be multiplexed through a common output if the channels are synchronized. The four channels share a common input clock and a common serial output clock, but the output sample rates can be synchronous or asynchronous. Bus multiplexers between the front end and back end sections provide flexible routing between channels for cascading back-end filters or for routing one front end to multiple back ends for polyphase filtering or systolic arrays (to provide wider bandwidth filtering). A level detector is provided to monitor the signal level on any of the parallel data input busses, facilitating microprocessor control of gain blocks prior to an A/D converter. Each front end NCO/digital mixer/CIC filter section includes a quadrature numerically controlled oscillator (NCO), digital mixer, barrel shifter and a cascaded-integrator-comb filter (CIC). The NCO has a 32-bit frequency control word for 22.1millihertz tuning resolution at an input sample rate of 95MSPS. The SFDR of the NCO is >115dB. The CIC filter order is programmable between 1 and 5 and the CIC decimation factor can be programmed from 4 to 512 for 5th order, 2048 for 4th order, 32768 for 3rd order, or 65536 for 1st or 2nd order filters. Each channel back end section includes an FIR processing block, an AGC and a cartesian-to-polar coordinate converter. The FIR processing block is a flexible filter compute engine that can compute a single FIR or a set of cascaded decimating, interpolating or resampling filters. A single filter in a chain can have up to 256 taps and the total number of taps in a set of filters can be up to 384 provided that the decimation is sufficient. The ISL5216 calculates two taps per clock (on each channel) for symmetric filters, generally making decimation the limiting factor for the number of taps available. The filter compute engine supports a variety of filter types including decimation, interpolation and resampling filters. The coefficients for the programmable digital filters are 22 bits wide. Coefficients are provided in ROM for several halfband filter responses and for a resampler. The AGC section can provide up to 96dB of either fixed or automatic gain control. For automatic gain control, two settling modes and two sets of loop gains are provided. Separate attack and decay slew rates are provided for each loop gain. Programmable limits allow the user to select a gain range less than 96dB. The outputs of the cartesian-to- polar coordinate conversion block, used by the AGC loop, are also provided as outputs to the user for AM and FM demodulation. The ISL5216 supports both fixed and floating point parallel data input modes. The floating point modes support gain ranging A/D converters. Gated, interpolated and multiplexed data input modes are supported. The serial data output word width for each data type can be programmed to one of ten output bit widths from 4-bit fixed point through 32-bit IEEE 754 floating point. The ISL5216 is programmed through a 16-bit microprocessor interface. The output data can also be read via the microprocessor interface for all channels that are synchronized. The ISL5216 is specified to operate to a maximum clock rate of 95MSPS over the industrial temperature range (-40oC to 85oC). The I/O power supply voltage range is 3.3V ± 0.165V while the core power supply voltage is 2.5V ± 0.125V. The I/Os are 5V tolerant. RD or RD/WR I Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode Control, µP MODE, is a low the data from the address specified is placed on P(15:0) when RD is asserted (low) and CE is asserted (low). When the µP MODE control is high this input functions as a Read/Write control input. Data is read from P(15:0) when high or written to the appropriate register when low. See Microprocessor Interface Section. µP MODE I Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the Microprocessor Interface. Internally pulled down. See Microprocessor Interface Section. CE I Microprocessor Interface Chip Select. Active low. This pin has the same timing as the address pins. INTRPT O Microprocessor Interrupt Signal. Asserted for a programmable number of clock cycles when new data is available on the selected Channel. Pin Descriptions (Continued) NAME TYPE DESCRIPTION ISL5216 |
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