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ISL29004 데이터시트(PDF) 7 Page - Intersil Corporation |
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ISL29004 데이터시트(HTML) 7 Page - Intersil Corporation |
7 / 17 page 7 FN6221.0 December 21, 2006 d Command Register 00(hex) The Read/Write command register has five functions: (1) Enable; Bit 7.This function either resets the ADC or enables the ADC in normal operation. A logic 0 disables ADC to reset-mode. A logic 1 enables adc to normal operation. (2) AdcPD; Bit 6. This function puts the device in a power down mode. A logic 0 puts the device in normal operation. A logic 1 powers down the device. (3) Timing Mode; Bit 5. This function determines whether the integration time is done internally or externally. In Internal Timing Mode, integration time is determined by an internal dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16) counter inside the ADC. In External Timing Mode, integration time is determined by the time between two consecutive external-sync sync_iic pules commands. (4) Photodiode Select Mode; Bits 3 and 2. This function controls the mux attached to the two photodiodes. At Mode0, the mux directs the current of Diode1 to the ADC. At Mode1, the mux directs the current of Diode2 only to the ADC. Mode3 is a sequential Mode0 and Mode1 with an internal subtract function (Diode1 - Diode2). * n = 4, 8, 12,16 depending on the number of clock cycles function. (5) Width; Bits 1 and 0. This function determines the number of clock cycles per conversion. Changing the number of clock cycles does more than just change the resolution of the device. It also changes the integration time, which is the period the device’s analog-to-digital (A/D) converter samples the photodiode current signal for a Lux measurement. Control Register 01(hex) The Read/Write control register has three functions: (1) Interrupt flag; Bit 5. This is the status bit of the interrupt. The bit is set to logic high when the interrupt thresholds have been triggered, and logic low when not yet triggered. Writing a logic low clears/resets the status bit. (2) Range/Gain; Bits 3 and 2. The Full Scale Range can be adjusted by an external resistor Rext and/or it can be adjusted via I2C using the Gain/Range funtion. Gain/Range has four possible values, Range(k) where k is 1 through 4. Table 9 lists the possible values of Range(k) and the resulting FSR for some typical value REXT resistors. When Gain/Range is set to Range1 or Range2, the fosc runs at 327kHz. When Gain/Range is set to Range3 or Range4 fosc runs at twice the rate at 655kHz. The automatic fosc adjustment feature improves signal-to-noise ratio for low Lux measurements. TABLE 2. WRITE ONLY REGISTERS ADDRESS REGISTER NAME FUNCTIONS/ DESCRIPTION b1xxx_xxxx sync_iic Writing a logic 1 to this address bit ends the current adc-integration and starts another. Used only with External Timing Mode. bx1xx_xxxx clar_int Writing a logic 1 to this address bit clears the interrupt. TABLE 3. ENABLE BIT 7 OPERATION 0 Disable ADC-core to reset-mode (default) 1 Enable ADC-core to normal operation TABLE 4. adcPD BIT 6 OPERATION 0 Normal operation (default) 1 Power Down TABLE 5. TIMING MODE BIT 5 OPERATION 0 Internal Timing Mode. Integration time is internally timed determined by fosc, REXT, and number of clock cycles. 1 External Timing Mode. Integration time is externally timed by the I2C host. TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3 BITS 3:2 MODE 0:0 Mode0. ADC integrates or converts Diode1 only. Current is converted to an n-bit unsigned data.* 0:1 Mode1. ADC integrates or coverts Diode2 only. Current is converted to an n-bit unsigned data.* 1:0 MODE3. A sequential Mode0 then Mode1 operation. The difference current is an (n-1) signed data.* 1:1 No operation. TABLE 7. WIDTH BITS 1:0 NUMBER OF CLOCK CYCLES 0:0 2^16 = 65,536 0:1 2^12 = 4,096 1:0 2^8 = 256 1:1 2^4 = 16 TABLE 8. INTERRUPT FLAG BIT 5 OPERATION 0 Interrupt is cleared or not triggered yet 1 Interrupt is triggered ISL29004 |
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