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FAN5601 데이터시트(PDF) 11 Page - Fairchild Semiconductor

부품명 FAN5601
상세설명  Regulated Step-Down Charge Pump DC/DC Converter
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN5601 데이터시트(HTML) 11 Page - Fairchild Semiconductor

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FAN5601 Rev. 1.0.5
Shutdown, UVLO, Short Circuit Current Limit
and Thermal Shutdown
The device has an active-low shutdown pin to decrease supply
current to less than 1
µA. In shutdown mode the supply is dis-
connected from the output. UVLO triggers when supply voltage
drops below 2V. When the output voltage is lower than 150mV, a
short circuit protection is triggered. In this mode 15 out of 16
pulses during the switching will be skipped and the supply cur-
rent is limited. Thermal shutdown triggers at 150°C.
Switch Configuration
Applications Information
Proper operation of the FAN5601 requires one ceramic bucket
capacitor in the 0.1µF to 1µF range; one 10µF output bypass
capacitor and one 10µF input bypass capacitor. In order to
obtain optimum output ripple and noise performance, use of low
ESR (<0.05
Ω) ceramic input and output bypass capacitors is
recommended. The X5R and X7R rated capacitors provide ade-
quate performance over the -40°C to 85°C temperature range.
The value of the bucket capacitor is dependent on load current
requirements. A 1µF bucket capacitor will work well in all appli-
cations at all load currents, while a 0.1µF capacitor will support
most applications under 100mA of load current. The choice of
bucket capacitor values should be verified in the actual applica-
tion at the lowest input voltage and highest load current. A 30%
margin of safety is recommended in order to account for the tol-
erance of the bucket capacitor and the variations in the on-resis-
tance of the internal switches.
S1
S2
S3
S4
V
IN
GND
C+
VOUT
C-
C
OUT
2:1 configuration
Switches in charging phase
Reverse all switches for pumping phase
C
B
S1
S3
S4
V
IN
GND
C+
VOUT
C-
C
OUT
1:1 configuration
Switch 3 is always off and
Switch 4 is always on
Switches 1 and 2 are in phase 1
Reverse the position of switches 1&2
for phase 2
C
B
S2
Figure 2. (A)
Figure 2. (B)


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