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TPA3107D2 데이터시트(PDF) 6 Page - Texas Instruments |
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TPA3107D2 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 36 page www.ti.com TPA3107D2 SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. ROUTP 53, 54 O Class-D 1/2-H-bridge positive output for right channel. PVCCR 45, 46 Power supply for right channel H-bridge, not connected to PVCCL or AVCC. BSRP 55 I/O Bootstrap I/O for right channel, positive high-side FET. AGND 7, 21 Analog ground for digital/analog cells in core. ROSC 18 I/O I/O for current setting resistor of ramp generator. Master/Slave select for determining direction of SYNC terminal. HIGH=Master MSTR/SLV 12 I mode, SYNC terminal is an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. Clock input/output for synchronizing multiple class-D devices. Direction determined SYNC 17 I/O by MSTR/SLV terminal. Input signal not to exceed VREG. Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time VBYP 20 O via external capacitor sizing. 4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins VREG 19 O only. Not specified for driving other external circuitry. AVCC 64 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL. 1-4, 13-16, 22-25, NC 32-34, 39, Not internally connected. 42, 47-49, 56-60 Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to AGND and PGND. Thermal vias on the PCB should Thermal Pad - - connect this pad to a large copper area on an internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the PCB for mechanical reliability. 6 Submit Documentation Feedback |
유사한 부품 번호 - TPA3107D2_07 |
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유사한 설명 - TPA3107D2_07 |
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