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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IRLR8503PBF 데이터시트(PDF) 3 Page - International Rectifier |
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IRLR8503PBF 데이터시트(HTML) 3 Page - International Rectifier |
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3 / 8 page  www.irf.com 3 IRLR8503PbF Device Capacitance Corresponding Charge Parameter C GS Q GS C GS + CGD Q G C GD Q GD Power MOSFET Optimization for DC-DC Converters While the IRLR8103V and IRLR8503 can and are be- ing used in a variety of applications, they were designed and optimized for low voltage DC-DC conversion in a synchronous buck converter topology, specifically, mi- croprocessor power applications. The IRLR8503 (Fig- ure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function. Because of the inter-electrode capacitance (Figure 2) of the Power MOSFET, specifying the R DSON of the de- vice is not enough to ensure good performance. An optimization between R DSON and charge must be per- formed to insure the best performing MOSFET for a given application. Both die size and device architec- ture must be varied to achieve the minimum possible in-circuit losses. This is independently true for both control FET and synchronous FET. Unfortunately, the capacitances of a FET are non-linear and voltage de- pendent. Therefore, it is inconvenient to specify and use them effectively in switching power supply power loss estimations. This was well understood years ago and resulted in changing the emphasis from capaci- tance to gate charge on Power MOSFET data sheets. International Rectifier has recently taken the industry a step further by specifying new charge parameters that are even more specific to DC-DC converter de- sign (Table 2). In order to understand these parameters, it is best to start with the in-circuit waveforms in Fig- ure 3 & Figure 4. Figure 1 – Application Topology Figure 2 – Inter-electrode Capacitance Table 1 – Traditional Charge Parameters Table 2 – New Charge Parameters Figure 3 – Control FET Waveform Figure 4 – Sync FET Waveform New Charge Parameter Description Waveform Q GS1 Pre-Threshold Gate Charge Q GS2 Post-Threshold Gate Charge Figure 3 Q GCONT Control FET Total Q G Q SWITCH Charge during control FET switching Combines Q GS2 and QGD Q OSS Output charge Figure 5 Charge supplied to C OSS during the QGD Figure 6 period of control FET switching Q GSYNC Synchronous FET Total Q G (VDS ≤ 0) Figure 4 The waveforms are broken into segments correspond- ing to charge parameters. These, in turn, correspond to discrete time segments of the switching waveform. Losses may be broken into four categories: conduc- tion loss, gate drive loss, switching loss, and output loss. The following simplified power loss equation is true for both MOSFETs in a synchronous buck con- verter: For the synchronous FET, the P SWITCH term becomes virtually zero and is ignored. P LOSS = PCONDUCTION + PGATE DRIVE + PSWITCH + POUTPUT Figure 5 – Q OSS Equivalent Circuit Figure 6 – Q OSS Waveforms Coss1 2n IRLR8503 (Cont FET) IRLR8103V (Sync FET) CGD CGS CDS Drain Voltage Gate Voltage Drain Current QGD VGTH QSwitch QG (Control FET) Drain Voltage 0 V Gate Voltage 0 A Drain Current Dead Time VGTH Body Diode Current QG (Sync FET) g1 g2 N1 Cont FET N2 Sync FET SN Coss2 2n VIN Switch node voltage (VSN) N1 Gate Voltage N1 Current N1 Coss Discharge + N2 Coss Charge |
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