AD7366/AD7367

Rev. 0 | Page 7 of 28

TIMING SPECIFICATIONS

otherwise noted.1

Table 4.

Parameter

Unit

Test Conditions/Comments

Conversion time, internal clock. CONVST falling edge to

BUSY falling edge

680

680

ns max

For the AD7367

610

610

ns max

For the AD7366

10

10

kHz min

Frequency of serial read clock

35

48

MHz max

30

30

ns min

Minimum quiet time required between the end of serial

read and the start of the next conversion

10

10

ns min

Minimum CONVST low pulse

40

40

ns min

CONVST falling edge to BUSY rising edge

0

0

ns min

BUSY going low

10

10

ns max

t52

20

14

ns max

Data access time after SCLK falling edge

7

7

ns min

SCLK to data valid hold time

ns min

SCLK low pulse width

ns min

SCLK high pulse width

10

10

ns max

70

70

μs

Power up time from shutdown mode; time required

between CONVST rising edge and CONVST falling edge

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the

Terminology section and Figure 25.