AD9910

Rev. 0 | Page 7 of 60

Parameter

Conditions/Comments

Min

Typ

Max

Unit

CMOS LOGIC INPUTS

Logic 1 Voltage

2.0

V

Logic 0 Voltage

0.8

V

Logic 1 Current

90

120

μA

Logic 0 Current

38

50

μA

Input Capacitance

2

pF

CMOS LOGIC OUTPUTS

1 mA load

Logic 1 Voltage

2.8

V

Logic 0 Voltage

0.4

V

POWER SUPPLY CURRENT

IAVDD (1.8 V)

110

mA

IAVDD (3.3 V)

29

mA

IDVDD (1.8 V)

222

mA

IDVDD (3.3 V)

11

mA

TOTAL POWER CONSUMPTION

Single Tone Mode

715

850

mW

Rapid Power-Down Mode

330

400

mW

Full Sleep Mode

19

25

mW

up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK

frequency is the same as the external reference clock frequency.