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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

SN74GTL16923

18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER

SCBS674G – AUGUST 1996 – REVISED APRIL 2005

Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA)

inputs. The clock-enable (CEAB and CEBA) inputs enable or disable the clock for all 18 bits at a time. However,

OEAB and OEBA are designed to control each 9-bit transceiver independently, which makes the device more

versatile.

For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB is

low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to

A is similar to that of A to B, but uses OEBA, CLKBA, and CEBA.

preventing damaging current backflow through the device when it is powered down.

Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown

resistors with the bus-hold circuitry is not recommended.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

TSSOP – DGG

Tape and reel

SN74GTL16923DGGR

GTL16923

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

INPUTS

OUTPUT

MODE

B

CEAB

OEAB

CLKAB

A

X

H

X

X

Z

Isolation

H

L

X

X

Latched storage of A data

X

L

H or L

X

L

L

↑

L

L

Clocked storage of A data

L

L

↑

H

H

(1)

A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, CLKBA, and CEBA.

(2)

Output level before the indicated steady-state input conditions were established

2