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5 / 8 page TND301 http://onsemi.com 5 Delay Lines Delay Lines are used to synchronize clocks that travel different distances within the Clock Management system (see Figure 7). It is difficult in the card cage with a backplane to distribute all clocks to all circuits using the same length line. The position of the cards in the card cage makes this impossible. One way to synchronize the clocks in a large system is to use delay line circuits. The signal comes into the device and is delayed by an amount determined by a programmable input. This programmable input can be a parallel word and/or a single analog voltage input. Figure 7. Example of Clock Delay 1 1 N Delay Line Device Short Lines Long Lines Programmable Input MC100EP195 MC100EP196 Clock Dividers Clock Dividers are required to reduce the frequency of certain clocks within a system. Figure 8. Example of Clock Division Divide by 2 MC100EP195 MC100LVEP34 MC100EP139 MC100EP016 Divide by 2 MC100EP33 MC100LVEP34 MC100EP139 MC100EP016 Divide by 2 MC100LVEP34 MC100EP016 |
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