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SA1638 데이터시트(PDF) 9 Page - NXP Semiconductors |
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SA1638 데이터시트(HTML) 9 Page - NXP Semiconductors |
9 / 26 page Philips Semiconductors Product specification SA1638 Low voltage IF I/Q transceiver 1997 Sept 03 9 divide by 64. The division ratio is binary coded and set in the registers n0 to n8. The default setting is a divide by 400. At the completion of a main divider cycle, a main divider output is generated which will drive the phase detector. Phase Detector The phase detector is a D-type flip-flop phase and frequency detector shown in Figure 5. The flip-flops are set by the negative edges of the output signals of the dividers. The rising edge of the signal L will reset the flip-flops after both flip-flops have been set. Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive on-chip charge pumps. A source current from the charge pump acts to increase the VCO frequency; a sink current acts to decrease the VCO frequency. Current Setting The charge pump current is defined by the current set between the pin IREF and VEECP. The current value to be set there is 31.2µA. This current can be set by an external resistor to be connected between the pin IREF and VEECP. The typical value REXT (current setting resistor) can be calculated with the formula R EXT + V CCCP * 1.4V 31.2 mA The current can be set to zero by connecting the pin IREF to VCCCP. Charge Pumps The charge pumps at pin CP are driven by the phase dectector and the current value is determined by the binary value of the charge pumps register CN = c2, c1, c0, default 1mA. The active charge pump current is typically: |I CP| + (c0 ) 2c1 ) 4c2) @ 71mA ) 500mA Lock Detect The output LOCK is H when the phase detector indicates a lock condition. This condition is defined as a phase difference of less than ±1 cycle on the reference input CLKIN, CLKINX. Test Modes (Synthesizer, Transmit Mixer) The LOCK output is selectable as a test output. Bits x0, x1 control the selection, the default setting is normal lock output as described in the Lock detect section. The selection of a Bit x0, x1 combination has a twofold effect: First it routes a divider output signal to the LOCK pin, second it disables mixer stages in the transmit path. Setting x0,1 = 11 disables both transmit path mixers. This mode can be used to prevent the transmitter from producing an IF output signal even if the transmit part is powered on (PDTx = 0V). This can be used to simplify the control timing while commanding the transmit and receive simultaneously without the transmit part causing interference. Table 1. Test Modes x0 x1 Synthesizer Signal Transmit Mixer x0 x1 yg at LOCK Pin Q-mixer I-mixer 0 0 normal lock detect on on 1 0 CLKIN divided by reference divider ratio off on 0 1 LOIN ÷ 2 * (main divider ratio) on off 1 1 main divider output, that goes to the phase detector off off Status Register The s0 and s1 status bits determine the values of the logic output pins AOUT and BOUT. These outputs can be connected to the AGC control inputs A and B of the SA1620. (See Figure 9) DC Offset Register Registers i0 to i3 and q0 to q3 control a correction to the output DC offset of the I and Q channels of the receiver. The polarity of the DC offset correction in the I and Q channels are determined by i0 and q0, respectively. The other bits set the magnitude of the offset correction. The step size of the two offset correction DACs is fixed by an external resistor between the DCRES pin and ground. A value of 120k Ω will give a step size of 200mV. Mode Select Register t0: switches the RX IF gain. t0 = 0 no attenuation t0 = 1 10dB attenuation The attenuation switch is included between the IF amplifier and the I and Q mixers, thereby influencing the noise figure negligibly. The purpose of this switch is to provide another AGC step which does not influence the receiver noise figure. Please note that this gain change will influence the DC offset of the I and Q mixers. t1 = 0 test mode only, always to be set to 0. t2, t3 sets the mode of the level locked loop (LLL) The LLL is a circuit which processes the LO input signal in order to provide an LO signal with a perfect 50% duty cycle, which determines the precision of the 90 ° shift of the I and Q mixing signals generated by the ÷2 divider. For an external tuning of the 90 ° phase shift of the I and Q mixing signals, a trimming resistor may be connected (but is not required) between the ADJIN pin and ground, and the LLL has to be put in one of the following modes: Table 2. Mode Select Register t2 t3 LLL Status 0 0 LLL on (no external tune, monitor performance, default) 0 1 LLL on (with medium external tune) 1 0 LLL off (tune externally) 1 1 LLL on (with fine external tune) t4 selects the bandwidth of the RC low pass filters at the I, Q Rx mixer outputs t4 = 0 cutt-off frequency (-3dB) 110kHz t4 = 1 cutt-off frequency (-3dB) 792kHz t5 selects the bandwidth of the integrated 5th-order gyrator filters. The filters are tuneable over a range of 50kHz to 1MHz with external resistors. The -3dB bandwidth is inversely proportional to the value of the external resistor. With t5, two external resistor values are selectable. t5 = 0 the resistance between the pins RESA and RESB determines the cutoff frequency. For GSM a nominal bandwidth of 80kHz is chosen when the external resistor is 36k Ω. t5 = 1 a second resistor between the pins RESB and RESD is connected in parallel to the first external resistor, thus increasing the filter bandwidth. The relative amplification is decreased in this mode. |
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