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TEA2164S 데이터시트(PDF) 7 Page - STMicroelectronics |
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TEA2164S 데이터시트(HTML) 7 Page - STMicroelectronics |
7 / 16 page SLAVE CIRCUIT MASTER CIRCUIT Sync. Pulses Pulse Input Base Current PWM Signal Synchronization Figure 5 : Master Slave Mode Waveforms II - GENERAL DESCRIPTION (continued) 9 10 TEA2164S P2 C1 Collector Current Envelop Voltage (Pin 10) Output Voltage 0t Soft Start 4V 1V θ Tb 0t 0t Tb 106 (C in Farad) C1 3.3 0.13 Tb θ 3.3 - 1.6 (V 9) t on T Max. Figure 6 : Burst Mode Waveforms II.3 - Power Supply Start-up After the mains have been switched-on, the VCC storage capacitor of the TEA2164S is charged through a high value resistor connected to the rectified high voltage. When Vcc reaches VCC start threshold (9V typ), the TEA2164 starts operating in burst mode. Since available output power is low in burst mode the output power consumption must remain low before complete setting-up of output voltage. In TV application it can be achieved by main- taining the TV in stand-by mode during start-up (Figure 7). TEA2164S 7/16 |
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