2001 Oct 01

4

Philips Semiconductors

Product specification

DVB-C channel receiver

TDA10021HT

PINNING

SYMBOL

PIN

DESCRIPTION

1

S

digital supply voltage for the core (1.8 V typ.)

XIN

2

I

XTAL oscillator input pin: a fundamental XTAL oscillator is connected between the

XIN and XOUT pins. The XTAL frequency must be chosen so that the system

frequency SYSCLK (XIN

× multiplying factor of the PLL) equals 1.6 times the tuner

output intermediate frequency; i.e. SYSCLK = 1.6

× IF.

XOUT

3

O

XTAL oscillator output pin: a fundamental XTAL oscillator is connected between the

XIN and XOUT pins

4

G

digital ground for the core

SACLK

5

O

sampling clock: this output clock can be fed to an external 10-bit ADC as the

sampling clock; SACLK = SYSCLK/2

TEST

6

I

test input pin: in normal mode, pin TEST must be connected to ground

7

S

digital supply voltage for the core (1.8 V typ.)

8

G

digital ground for the core

AGCTUN

9

O/OD

first PWM encoded output signal for AGC tuner: this signal is fed to the AGC

amplifier through a single RC network. The maximum signal frequency on the

VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.

IICDIV

10

I

AGCIF

11

O/OD

second PWM encoded output signal for the AGC IF: This signal is fed to the AGC

amplifier through a single RC network. The maximum signal frequency on the

VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.

However AGCIF can also be configured to output a PWM signal, the value of which

SADDR

12

I

TDA10021HT is (MSB to LSB) 0, 0, 0, 1, 1, 0 and SADDR.

13

S

digital supply voltage for the pad 5.0 V (necessary for 5 V tolerant inputs)

14

S

digital supply voltage for the pads (3.3 V typ.)

15

G

digital ground for the pads

CLR#

16

I

the CLR# input is asynchronous and active LOW, and clears the TDA10021HT:

When CLR# goes LOW, the circuit immediately enters its reset mode and normal

register contents are all initialized to their default values. The minimum width of

CLR# at LOW level is 4 XIN clock periods.

SCL

17

I

SDA

18

I/OD

A pull-up resistor (typically 4.7 k

proper operation (open-drain output).

SDAT

19

I/OD

programming. It is actually the output of a switch controlled by parameter BYPIIC of

register TEST (index 0F). SDAT is an open-drain output and therefore requires an

external pull-up resistor.