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SST49LF008A 데이터시트(PDF) 9 Page - Silicon Storage Technology, Inc |
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SST49LF008A 데이터시트(HTML) 9 Page - Silicon Storage Technology, Inc |
9 / 42 page Data Sheet 8 Mbit Firmware Hub SST49LF008A 9 ©2006 Silicon Storage Technology, Inc. S71161-11-000 3/06 TABLE 1: Pin Description Symbol Pin Name Type1 Interface Functions PP FWH A10-A0 Address I X Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the pro- gramming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs. DQ7-DQ0 Data I/O X To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The out- puts are in tri-state when OE# is high. OE# Output Enable I X To gate the data output buffers WE# Write Enable I X To control the Write operations IC Interface Configuration Pin I X X This pin determines which interface is operational. When held high, programmer mode is enabled and when held low, FWH mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin is internally pulled- down with a resistor between 20-100 K Ω. INIT# Initialize I X This is the second reset pin for in-system use. This pin is internally combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited. ID[3:0] Identification Inputs I X These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component.The boot device must have ID[3:0]=0000 and it is recommended that all subsequent devices should use sequential up-count strapping. These pins are internally pulled-down with a resistor between 20-100 K Ω. FGPI[4:0] General Purpose Inputs I X These individual inputs can be used for additional board flexibility. The state of these pins can be read through GPI_REG register. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. TBL# Top Block Lock I X When low, prevents programming to the Boot Block sectors at top of memory. When TBL# is high it disables hardware write protection for the top block sectors. This pin cannot be left unconnected. FWH[3:0] FWH I/Os I/O X I/O Communications CLK Clock I X To provide a clock input to the control unit FWH4 FWH Input I X Input Communications RST# Reset I X X To reset the operation of the device WP# Write Protect I X When low, prevents programming to all but the highest addressable blocks. When WP# is high it disables hardware write protection for these blocks. This pin cannot be left unconnected. R/C# Row/Column Select I X Select For the Programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. RES Reserved X These pins must be left unconnected. VDD Power Supply PWR X X To provide power supply (3.0-3.6V) VSS Ground PWR X X Circuit ground (OV reference) All VSS pins must be grounded. NC No Connection I X X Unconnected pins T1.4 1161 1. I = Input, O = Output |
유사한 부품 번호 - SST49LF008A_06 |
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유사한 설명 - SST49LF008A_06 |
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