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SST32HF64A2-70-4E-L1PE 데이터시트(PDF) 4 Page - Silicon Storage Technology, Inc

부품명 SST32HF64A2-70-4E-L1PE
상세설명  Multi-Purpose Flash Plus PSRAM ComboMemory
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제조업체  SST [Silicon Storage Technology, Inc]
홈페이지  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

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Preliminary Specifications
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
©2006 Silicon Storage Technology, Inc.
S71299-02-000
11/06
Flash Data# Polling (DQ7)
When the SST32HF64A2 flash memory banks are in the
internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Pro-
gram operation is complete, DQ7 will produce true data.
However, even though DQ7 may have valid data immedi-
ately following the completion of an internal Write opera-
tion, the remaining data outputs may still be invalid. Valid
data on the entire data bus will appear in subsequent suc-
cessive Read cycles after an interval of 1 µs.
During internal Erase operation, any attempt to read DQ7
will produce a ‘0’. Once the internal Erase operation is
complete, DQ7 will produce a ‘1’. The Data# Polling is valid
after the rising edge of the fourth WE# (or BEF#) pulse for
Program operation. For Sector- or Block-Erase, the Data#
Polling is valid after the rising edge of the sixth WE# (or
BEF#) pulse. See Figure 10 for Data# Polling timing dia-
gram and Figure 24 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 bit will alternate between ‘1’
and ‘0’. When the internal Program or Erase operation is
complete, the DQ6 bit will stop toggling. The device is then
ready for the next operation.
For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is
valid after the rising edge of sixth WE# (or BEF#) pulse.
DQ6 will be set to ‘1’ if a Read operation is attempted on an
Erase-Suspended Sector/Block. If a Program operation is
initiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which is used
in conjunction with DQ6 to check whether a particular sec-
tor is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or
BEF#) pulse of Write operation. See Figure 11 for Toggle
Bit timing diagram and Figure 24 for a flowchart.
Note: DQ7 and DQ2 require a valid address when reading
status information.
Flash Memory Data Protection
The SST32HF64A2 flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
TABLE
1: Write Operation Status
Status
DQ7
DQ6
DQ2
Normal
Operation
Standard
Program
DQ7#
Toggle
No Toggle
Standard
Erase
0
Toggle
Toggle
Erase-
Suspend
Mode
Read from
Erase-Suspended
Sector/Block
1
1
Toggle
Read from
Non- Erase-Suspended
Sector/Block
Data
Data
Data
Program
DQ7#
Toggle
N/A
T1.0 1299


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