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TDA8002CG 데이터시트(PDF) 8 Page - NXP Semiconductors |
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TDA8002CG 데이터시트(HTML) 8 Page - NXP Semiconductors |
8 / 28 page 1999 Oct 12 8 Philips Semiconductors Product specification IC card interface TDA8002C FUNCTIONAL DESCRIPTION Power supply The supply pins for the chip are VDDA, VDDD, AGND, DGND1 and DGND2. VDDA and VDDD (i.e. VDD) should be in the range of 3.0 to 6.5 V. All card contacts remain inactive during power-up or power-down. On power-up, the logic is reset by an internal signal. The sequencer is not activated until VDD reaches Vth2 +Vhys2 (see Fig.6). When VDD falls below Vth2, an automatic deactivation sequence of the contacts is performed. Chip selection The chip select pin (CS) allows the use of several TDA8002Cs in parallel. When CS is HIGH, the pins RSTN, CMDVCC, MODE, CV/TV, CLKDIV1, CLKDIV2, CLKSEL and STROBE control the chip, pins I/OUC, AUX1UC and AUX2UC are the copy of I/O, AUX1 and AUX2 when enabled (with integrated 20 k Ω pull-up resistors connected to VDD) and OFF is enabled. When CS goes LOW, the levels on pins RSTIN, CMDVCC, MODE, CV/TV, CLKDIV1, CLKDIV2 and STROBE are internally latched, I/OUC, AUX1UC and AUX2UC go to high-impedance with respect to I/O, AUX1 and AUX2 (with integrated 100 k Ω pull-up resistors connected to VDD) and OFF is high-impedance. Supply voltage supervisor (VDD) This block surveys the VDD supply. A defined retriggerable pulse of 10 ms minimum (tW) is delivered on the ALARM output during power-up or power-down of VDD (see Fig.6). This signal is also used for eliminating the spikes on card contacts during power-up or power-down. When VDD reaches Vth2 +Vhys2, an internal delay (tW) is started. The ALARM output is active until this delay has expired. When VDD falls below Vth2, ALARM is activated and a deactivation sequence of the contacts is performed. Clock circuitry The TDA8002C supports both synchronous and asynchronous cards. There are three methods to clock the circuitry: • Apply a clock signal to pin STROBE • Use of an internal RC oscillator • Use of a quartz oscillator which should be connected between pins XTAL1 and XTAL2 or an external clock applied on XTAL1. When CLKSEL is HIGH, the clock should be applied to the STROBE pin. When CLKSEL is LOW, the internal oscillators is used. When an internal clock is used, the clock output is available on pin CLKOUT. The RC oscillator is selected by making CLKDIV1 HIGH and CLKDIV2 LOW. The clock output to the card is available on pin CLK. The frequency of the card clock can be the input frequency divided by 2 or 4, STOP low or 1.25 MHz, depending on the states of CLKDIV1 or CLKDIV2 (see Table 1). When STROBE is used for entering the clock to a synchronous card, STROBE should remain stable during activation sequence otherwise the first pulse may be omitted. Do not change CLKSEL during activation. When in low-power (sleep) mode, the internal oscillator frequency which is available on pin CLKOUT is lowered to approximately 16 kHz for power economy purposes. |
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