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TC72-5.0MUATR 데이터시트(PDF) 10 Page - Microchip Technology

부품명 TC72-5.0MUATR
상세설명  Digital Temperature Sensor with SPI??Interface
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
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TC72
DS21743A-page 10
 2002 Microchip Technology Inc.
TABLE 3-3:
OPERATIONAL MODES
3.4
Read Operation
The temperature and control register data is outputted
from the TC72 using the CE, SCK and SDO lines.
Figure 3-3 shows a timing diagram of the read opera-
tion. Communication is initiated by the chip enable (CE)
going high. The SDO line remains at the voltage level
of the LSb bit that is outputted and goes to the tri-state
level when the CE line goes to a logic low level.
3.5
Write Operation
Data is clocked into the Control register in order to
enable the TC72’s power saving shutdown mode. The
write operation is shown in Figure 3-3 and is
accomplished using the CE, SCK and SDI line.
FIGURE 3-2:
Serial Clock Polarity (CP)
Operation.
Mode
CE
SCK (Note 1)
SDI
SDO
Disable
L
Input Disabled
Input Disabled
High Z
Write (A7 = 1)H
CP=1, Data Shifted on Falling Edge,
Data Clocked on Rising Edge
Data Bit Latch
High Z
CP=0, Data Shifted on Rising Edge,
Data Clocked on Falling Edge
Read (A7 = 0)H
CP=1, Data Shifted on Falling Edge,
Data Clocked on Rising Edge
X
Next data bit shift,
Note 2
CP=0, Data Shifted on Rising Edge,
Data Clocked on Falling Edge
Note 1: CP is the Clock Polarity of the microcontroller system clock. If the inactive state of SCK is logic level high,
CP is equal to ‘1’; otherwise, if the inactive state of SCK is low, CP is equal to ‘0’.
2: During a Read operation, SDO remains at a high impedance (High Z) level until the eight bits of data begin
to be shifted out of the Temperature register.
SHIFT
EDGE
CLOCK
EDGE
SHIFT
EDGE
CLOCK
EDGE
SCK
CE
CE
SCK
CP = 0
CP = 1


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