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93AA56A 데이터시트(PDF) 7 Page - Microchip Technology

부품명 93AA56A
상세설명  2K Microwire Compatible Serial EEPROM
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

93AA56A 데이터시트(HTML) 7 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
DS21794E-page 7
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.4
Erase
The ERASE instruction forces all data bits of the speci-
fied address to the logical ‘1’ state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
FIGURE 2-1:
ERASE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
TCSL
Check Status
11
1
AN
AN-1
AN-2
•••
A0
TSV
TCZ
Busy
Ready
High-Z
TWC
High-Z
CS
CLK
DI
DO
TCSL
Check Status
11
1
AN
AN-1
AN-2
•••
A0
TSV
TCZ
Busy
Ready
High-Z
TWC
High-Z


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