TS5A26542 datasheet(3/21 Pages) TI

부품명	TS5A26542

상세설명	0.75-W DUAL SPDT ANALOG SWITCH WITH INPUT LOGIC TRANSLATION

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Electrical Characteristics for 5-V Supply

(1)

TS5A26542

0.75-

Ω DUAL SPDT ANALOG SWITCH

WITH INPUT LOGIC TRANSLATION

SCDS232B – JUNE 2006 – REVISED APRIL 2007

V

+ = 4.5 V to 5.5 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)

PARAMETER

SYMBOL

TEST CONDITIONS

TA

V+

MIN

TYP

MAX

UNIT

Analog Switch

VCOM,

Analog signal range

0

V+

V

VNO

25

°C

0.5

0.75

VNO or VNC = 2.5 V,

Switch ON,

ON-state resistance

ron

4.5 V

Ω

ICOM = –100 mA,

See Figure 14

Full

0.8

ON-state resistance

25

°C

0.05

0.1

VNO or VNC = 2.5 V,

Switch ON,

match between

∆r

on

4.5 V

Ω

ICOM = –100 mA,

See Figure 14

Full

0.1

channels

0

≤ (V

NO or VNC) ≤ V+,

Switch ON,

25

°C

0.1

ICOM = –100 mA,

See Figure 14

ON-state resistance

ron(flat)

4.5 V

Ω

VNO or VNC = 1 V, 1.5 V,

25

°C

0.1

0.25

flatness

Switch ON,

2.5 V,

See Figure 14

Full

0.25

ICOM = –100 mA,

VNO = 1 V, 4.5 V,

25

°C

–20

2

20

VCOM = 4.5 V, 1 V,

NO, NC

VNC = Open,

INO(OFF),

Switch OFF,

OFF leakage

or

5.5 V

nA

INC(OFF)

See Figure 15

Full

–100

100

current

VNC = 1 V, 4.5 V,

VCOM = 4.5 V, 1 V,

VNO = Open,

VNO = 1 V, 4.5 V,

25

°C

–20

2

20

VNC and VCOM = Open,

NC, NO

Switch ON,

INO(ON)

or

5.5 V

nA

ON leakage current

See Figure 16

Full

–200

200

VNC = 1V, 4.5 V,

VNO and VCOM = Open,

VCOM = 1 V,

25

°C

–20

2

20

VNO and VNC = Open,

COM

ICOM(ON)

or

See Figure 16

5.5 V

nA

ON leakage current

Full

–200

200

VCOM = 4.5 V,

VNO and VNC = Open,

Digital Control Inputs (IN1, IN2)(2)

Input logic high

VIH

VIO = 1.65 V to 1.95 V

Full

0.65

× V

IO

VIO

V

Input logic low

VIL

VIO = 1.65 V to 1.95 V

Full

0

0.35

× V

IO

V

25

°C

–2

2

Input leakage

IIH, IIL

VI = VIO or 0

5.5 V

nA

current

Full

–20

20

(1)

The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum

(2)

All unused digital inputs of the device must be held at VIO or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

3

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