11

STK17TA8

March 2007

Document Control #ML0025 Rev 1.5

MODE SELECTION

E

W

G

Mode

I/O

Power

Notes

H

X

X

X

Not Selected

Output High Z

Standby

L

H

L

X

Read SRAM

Output Data

Active

L

L

X

X

Write SRAM

Input Data

Active

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8FC0

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Store

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

q,r,s

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Recall

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

q,r,s

Notes

q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

r: While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes

s: I/O state depends on the state of G. The I/O table shown assumes G low