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TDA8779H 데이터시트(PDF) 8 Page - NXP Semiconductors |
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TDA8779H 데이터시트(HTML) 8 Page - NXP Semiconductors |
8 / 20 page 1996 Sep 18 8 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 ANALOG SIGNAL PROCESSING Linearity INLA integral non linearity ramp input; fCLK =20MHz −±2 − LSB DNLA differential non linearity full-scale; ramp input; fCLK =20MHz −±0.5 − LSB 50% full-scale; ramp input; fCLK =20MHz −±0.3 − LSB Noise floor; note 2 NF noise floor fin = 5.1 MHz; 20 Msps −−60 − dB Harmonics; note 3 THD total harmonic distortion fi = 5.1 MHz; 20 Msps −−54 − dB Spurious free dynamic range SFDR spurious free dynamic range fi = 5.1 MHz; 20 Msps 45 56 − dB Matching between the I and Q channels ∆V amplitude matching fin = 5.1 MHz; fCLK = 20 MHz; Tamb =25°C −− 6% ∆ϕ phase matching fin = 5.1 MHz; fCLK = 20 MHz; Tamb =25°C −− 2 Deg Bandwidth B bandwidth maximum attenuation of −0.3 dB full-scale sine wave; Tamb =25°C; 5.5 −− MHz 50% full-scale sine wave; Tamb =25°C; tbf −− MHz TIMING:(THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME td); CL = 15 pF; see Fig.3 tds sampling delay time −− 5ns th output hold time 5 −− ns td output delay time VCCO = 4.75 V − 12 15 ns VCCO = 3.15 V − 17 20 ns VCCO = 2.7 V − 21 24 ns 3-STATE OUTPUT DELAY TIMES; see Fig.4 tdZH output delay enable HIGH − 14 18 ns tdZL output delay enable LOW − 16 20 ns tdHZ output delay disable HIGH − 16 20 ns tdLZ output delay disable LOW − 14 18 ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
유사한 부품 번호 - TDA8779H |
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유사한 설명 - TDA8779H |
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