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P93U422 데이터시트(Datasheet) 3 Page - Pyramid Semiconductor Corporation

부품명 P93U422
상세내용  HIGH SPEED 256 x 4 STATIC CMOS RAM
PDF  10 Pages
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제조사  PYRAMID [Pyramid Semiconductor Corporation]
홈페이지  http://www.pyramidsemiconductor.com
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P93U422
Page 3 of 10
Document # SRAM102 REV A
Mode
CS
2
CS
CS
CS
CS
CS
1
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Output
Standby
L
X
X
X
High Z
Standby
X
H
X
X
High Z
D
OUT Disabled
H
L
X
H
High Z
Read
H
L
H
L
D
OUT
Write
H
L
L
X
High Z
t
S(DI)
t
PLZ (WE)
(8)
t
PHZ (WE)
(8)
TRUTH TABLE
recovery times by eliminating the “write recovery glitch.”
Reading is performed with chip selct one (CS
1) LOW, chip
select two (CS
2) HIGH, write enable
(WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O
0 through O3). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS
1) is HIGH, or during the write operation when write
enable (WE) is LOW.
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When chip select one
(CS
1) and write enable (WE) are LOW and chip select two
(CS
2) is HIGH, the information on data inputs (D0 through
D
3) is written into the addressed memory word and
preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
FUNCTIONALDESCRIPTION
SWITCHING CHARACTERISTICS (5,6)
Over Operating Range (Commercial and Military)
Notes: H = HIGH
L = Low
X = Don't Care
HIGH Z = Implies outputs are disabled or off. This
condition is defined as high impedance state
for the P93U422.
Unit
ns
Parameters
t
PLH(A)
(7)
t
PLH(A)
(7)
t
PZH (CS1, CS2)
(8)
t
PZL (CS1, CS2)
(8)
t
PZH (WE)
(8)
t
PZL (WE)
(8)
t
PZH (OE)
(8)
t
PZL (OE)
(8)
t
S(A)
t
h(DI)
t
S (CS1, CS2)
t
h (CS1, CS2)
t
pw(WE)
t
PHZ (CS1, CS2)
(8)
t
PLZ (CS1, CS2)
(8)
t
PHZ (OE)
(8)
t
PLZ (OE)
(8)
Description
Delay from Address to Output (Address Access Time) (See Fig. 2)
Delay from Chip Select to Active Output and Correct Data (See Fig. 2)
Delay from Write Enable to Active Output and Correct Data (Write Recovery)
(See Fig. 1)
Delay from Output Enable to Active Output and Correct Data (See Fig. 2)
Setup Time Address (Prior to Initiation of Write) (See Fig. 1)
Hold Time Address (After Termination of Write) (See Fig. 1)
Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1)
Hold Time Data Input (After Termination of Write) (See Fig. 1)
Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1)
Hold Time Chip Select (After Termination of Write) (See Fig. 1)
Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1)
Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2)
Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1)
Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2)
P93U422
5
5
5
5
5
5
20
Max.
Min.
35
25
25
25
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
h(A)




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