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CS8416-CZZ 데이터시트(PDF) 10 Page - Cirrus Logic |
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CS8416-CZZ 데이터시트(HTML) 10 Page - Cirrus Logic |
10 / 60 page 10 DS578F3 CS8416 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Notes: 12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dic- tated by the timing requirements necessary to access the Channel Status memory. Access to the con- trol register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions. 13. Data must be held for sufficient time to bridge the transition time of CCLK. 14. For fsck <1 MHz. Parameter Symbol Min Max Unit CCLK Clock Frequency (Note 12) fsck 06.0 MHz CS High Time Between Transmissions tcsh 1.0 - µs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 13) tdh 15 - ns CCLK Falling to CDOUT Stable tpd -50 ns Rise Time of CDOUT tr1 -25 ns Fall Time of CDOUT tf1 -25 ns Rise Time of CCLK and CDIN (Note 14) tr2 -100 ns Fall Time of CCLK and CDIN (Note 14) tr2 -100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh Figure 3. SPI Mode Timing |
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