전자부품 데이터시트 검색엔진 |
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SI5316 데이터시트(PDF) 8 Page - Silicon Laboratories |
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SI5316 데이터시트(HTML) 8 Page - Silicon Laboratories |
8 / 16 page Si5316 8 Preliminary Rev. 0.24 7 6 XB XA IAnalog External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. If external reference is used, apply refer- ence clock to XA input and leave XB pin floating. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pin. 8, 31 GND GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. 15 RATE I 3-Level External Crystal or Reference Clock Rate. Three level input that selects the type and rate of external crystal or reference clock to be applied to the XA/XB port. L = 38.88 MHz external clock M = 114.285 MHz 3rd OT crystal H= Reserved 12 13 CKIN2+ CKIN2– IMulti Clock Input 2. Differential input clock. This input can also be driven with a single- ended signal. 14 DBL_BY I 3-Level Output Disable/Bypass Mode Control. Controls enable of CKOUT divider/output buffer path and PLL bypass mode. L = CKOUT enabled M = CKOUT disabled H = Bypass mode with CKOUT enabled 16 17 CKIN1+ CKIN1– IMulti Clock Input 1. Differential input clock. This input can also be driven with a single- ended signal. 18 LOL O LVCMOS PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator. 0=PLL locked 1 = PLL unlocked 21 CS I LVCMOS Input Clock Select. This pin functions as the input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CKSEL input state. 0 = Select CKIN1 1 = Select CKIN2 23 22 BWSEL1 BWSEL0 I 3-Level Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual. 25 24 FRQSEL1 FRQSEL0 I 3-Level Frequency Select. Sets the output frequency of the device. When the frequency of CKIN1 is not equal to CKIN2, the lower frequency input clock must be equal to the output clock frequency. Table 3. Si5316 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description |
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