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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SST39WF800A-90-4C-M2KE 데이터시트(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST39WF800A-90-4C-M2KE 데이터시트(HTML) 2 Page - Silicon Storage Technology, Inc |
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2 / 27 page  2 Data Sheet 8 Mbit Multi-Purpose Flash SST39WF800A ©2006 Silicon Storage Technology, Inc. S71258-06-000 07/07 Device Operation Commands are used to initiate the memory operation func- tions of the device. Commands are written to the device using standard microprocessor write sequences. A com- mand is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39WF800A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Word-Program Operation The SST39WF800A is programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Pro- gram operation, once initiated, will be completed within 40 µs. See Figures 5 and 6 for WE# and CE# controlled Pro- gram operation timing diagrams and Figure 17 for flow- charts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Pro- gram operation, the host is free to perform additional tasks. Any commands issued during the internal Program opera- tion are ignored. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST39WF800A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector- Erase operation is initiated by executing a six-byte com- mand sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of- Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sec- tor- or Block-Erase operation are ignored. Chip-Erase Operation The SST39WF800A provides a Chip-Erase operation, which allows the user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 20 for the flowchart. Any commands issued dur- ing the Chip-Erase operation are ignored. |
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