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FM25L256B-G 데이터시트(PDF) 5 Page - Ramtron International Corporation

부품명 FM25L256B-G
상세설명  256Kb FRAM Serial 3V Memory
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제조업체  RAMTRON [Ramtron International Corporation]
홈페이지  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM25L256B-G 데이터시트(HTML) 5 Page - Ramtron International Corporation

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FM25L256B
Rev. 3.0
July 2007
Page 5 of 14
Power Up to First Access
The FM25L256B is not accessible for a period of
time (10 ms) after power up.
Users must comply
with the timing parameter tPU, which is the minimum
time from VDD (min) to the first /CS low.
Data Transfer
All data transfers to and from the FM25L256B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L256B. They
are listed in the table below. These op-codes control
the functions performed by the memory. They can be
divided
into
three
categories.
First,
there
are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-Code Commands
Name
Description
Op-Code
WREN
Set Write Enable Latch
0000 0110b
WRDI
Write Disable
0000 0100b
RDSR
Read Status Register
0000 0101b
WRSR
Write Status Register
0000 0001b
READ
Read Memory Data
0000 0011b
WRITE
Write Memory Data
0000 0010b
WREN - Set Write Enable Latch
The FM25L256B will power up with writes
disabled. The WREN command must be issued prior
to any write operation. Sending the WREN op-code
will allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1
indicates
that
writes
are
permitted.
Attempting to write the WEL bit in the status
register has no effect on the state of this bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below
illustrates
the
WREN
command
bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Hi-Z
0
1
2
3
4
5
6
7
0
0
0
0
0
1
1
0
CS
SCK
SI
SO
Figure 5. WREN Bus Configuration


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